In parts 1 and 2 of the webinar series on “Practical Aspects of Signal Integrity”, an expert provided the basic design concepts to consider when laying out a board for high speed signals to ensure the signal’s integrity. If you missed it, we encourage you to watch the recordings of these webinars. The concepts presented build upon each other so we feel you will find it very beneficial.
In Part 3 of this webinar series, our expert, Tom Cassidy, will present the simulation and analysis of a functional FPGA-based DDR3 memory design. In addition, he will examine some of the common layout paradigms inherent to DDR3 and explore their signal integrity implications.
- Xilinx Zynq FPGA and Micron DDR3 Memory
- “Power-aware” Simulation and Analysis
- JEDEC Compliance Reports
- Signal Termination
- Differential Pair Routing Concerns
- Alternate Routing Paradigms
Although this webinar will be using a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts are applicable to any tier-one analysis tool. Click HERE to watch Part 3 of the webinar series, “Practical Aspects of Signal Integrity”.
Have questions and want to talk to an expert? Click HERE and someone from The SolidExperts will be happy to assist you.